Boot Modes

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The BootROM can boot the system from Quad-SPI, SD, eMMC, USB 2.0 controller 0, or NAND external boot devices.

Note:   The flash memory devices for boot are listed in Answer Record 65463. For SD and eMMC devices, the JEDEC interface specified in SD/SDIO/eMMC Controller is supported. For Quad-SPI and NAND, specific devices are tested and supported.

 

IMPORTANT:   If you use NAND as the primary boot device, only use NAND devices from a vendor that guarantees screening for zero data corruption on the first parameter page.

Table: Boot Modes describes various boot modes. All modes can be non-secure. All modes can be secure and signed except PS JTAG and PJTAG.

Table 11-1:      Boot Modes

Boot Mode

Mode Pins
[3:0]

Pin Location

CSU Mode

Description

PS JTAG

0000

JTAG

Slave

PSJTAG interface, PS dedicated pins.

Quad-SPI (24b)

0001

MIO[12:0]

Master

24-bit addressing (QSPI24).

Quad-SPI (32b)

0010

MIO[12:0]

Master

32-bit addressing (QSPI32).

SD0 (2.0)

0011

MIO[25:21, 16:13]

Master

SD 2.0.

NAND

0100

MIO[25:09]

Master

Requires 8-bit data bus width.

SD1 (2.0)

0101

MIO[51:43]

Master

SD 2.0.

eMMC (1.8V)

0110

MIO[22:13]

Master

eMMC version 4.5 at 1.8V.

USB0 (2.0)

0111

MIO[52:63]

Slave

USB 2.0 only.

PJTAG (MIO #0)

1000

MIO[29:26]

Slave

PJTAG connection 0 option.

PJTAG (MIO #1)

1001

MIO[15:12]

Slave

PJTAG connection 1 option.

SD1 LS (3.0)

1110

MIO[51:39]

Master

SD 3.0 with a required SD 3.0 compliant voltage level shifter.

Quad-SPI (24b/32b): The BootROM code can boot Quad-SPI using 24- or 32-bit addressing using the configurations shown in Table: Quad-SPI I/O Configurations.

The QSPI boot mode size limit and image search limit are listed in Table: Boot Image Search Limits. Image search for multi-boot is supported in this boot mode. The QSPI boot mode also supports x1, x2 and x4 read modes for single Quad-SPI memory and x8 for a dual QSPI. This is the only boot mode that supports execute-in-place (XIP).

Table: Boot Image Search Limits shows the boot modes supporting image search along with the search offset limit.

Table 11-2:      Boot Image Search Limits

Boot Mode

Search Offset Limit

QSPI: 24-bit single

16 MB

QSPI: 24-bit dual parallel

32 MB

QSPI: 32 bit

256 MB

QSPI: 32-bit dual parallel

512 MB

NAND

128 MB

SD/eMMC

8,191 files

USB

1 file

 

RECOMMENDED:   Xilinx recommends using the QSPI 32-bit boot mode for flash sizes larger than 16 MB and when the flash supports 32-bit addressing.

 

RECOMMENDED:   Xilinx recommends that verifying the QSPI commands supported by a specific flash memory. The CSU ROM supports the QSPI commands listed in Table: QSPI Command Codes.

Table 11-3:      QSPI Command Codes

Quad-SPI Data Interface

Read Mode

Command Code

24-bit single

Normal read

0x03

24-bit dual

Output fast read

0x3B

24-bit quad

Output fast read

0x6B

32-bit boot

Normal read

0x13

32-bit dual

Output fast read

0x3C

32-bit quad

Output fast read

0x6C

NAND: The NAND boot mode only supports 8-bit widths for reading the boot images. Image search for multi-boot is supported. Boot mode image search limits are listed in Table: Boot Image Search Limits.

SD0/SD1: These boot modes support FAT 16/32 file systems for reading the boot images. Image search for multi-boot is supported. The maximum number of files that can be searched as part of an image search for multi-boot are 8,191. The SD supported version is 2.0, which only supports 3.3V for the I/Os and up to 4 bits of data interface.

SD1(LS): The SD1-LS boot mode is the same as SD0/SD1 with additional support of the SD 3.0 (with an SD 3.0 compliant voltage level shifter).

eMMC(18): This boot mode is the same as the SD boot mode except it only supports 1.8V for the I/Os and up to 8 bits of data interface. The eMMC mode is used for eMMC interfacing and the SD0/1 mode is used for SD card only. The application must switch to the high-speed modes.

 

TIP:   For SD and eMMC boot modes, the boot image file should be at the root of first partition of the SD card (not inside any directory).

USB0: The USB boot mode configures USB controller 0 into device mode and uses the Device Firmware Upgrade (DFU) protocol to communicate with an attached host. See the “Boot Sequence for USB Boot Mode” section in Zynq UltraScale+ MPSoC: Embedded Design Tutorial (UG1209) [Ref 17] for more information.

The USB host contains the FSBL boot image (e.g., boot.bin) that is loaded into OCM memory for the CSU BootROM code and an all encompassing boot image file (e.g., boota53_all.bin) that is loaded into DDR memory.

The size of these files are limited by the size of the OCM and DDR memories. The USB boot mode does not support multi-boot, image fallback, or XIP.

Note:   USB Timeout Condition - When the Zynq UltraScale+ MPSoC powers up in the USB boot mode, the USB host can download the boot image to the Zynq UltraScale+ MPSoC memory through the USB interface in DFU protocol. However during a time out of approximately five minutes in CSU ROM code, no image is downloaded and the host will not able to locate the DFU device with DFU utility.