Bridge Core Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The bridge core registers program the bridge features and apertures for various access regions. Table: Bridge Core Registers summarizes the bridge core registers.

Table 30-11:      Bridge Core Registers

Register Name

Description

BRIDGE_CORE_CFG_PCIE_RX0

PCI Express receive access and BAR configuration.

BRIDGE_CORE_CFG_PCIE_RX1

PCI Express receive transaction attribute handling.

BRIDGE_CORE_CFG_AXI_MASTER

AXI master maximum payload size configuration.

BRIDGE_CORE_CFG_PCIE_TX

PCI Express transmit cut through configuration.

BRIDGE_CORE_CFG_INTERRUPT

PCI Express core interrupt routing configuration.

BRIDGE_CORE_CFG_RAM_DISABLE0

ECC RAM 1-bit error correction enable/disable (designs with ECC support only).

BRIDGE_CORE_CFG_RAM_DISABLE1

ECC RAM 2-bit error handling enable/disable (designs with ECC support only).

BRIDGE_CORE_CFG_PCIE_RELAXED_ORDER

PCI Express receive completion ordering configuration.

BRIDGE_CORE_CFG_PCIE_RX_MSG_FILTER

PCI Express receive message filtering configuration.

BRIDGE_CORE_CFG_RQ_REQ_ORDER

PCI Express and AXI read reorder queue completion ordering configuration.

BRIDGE_CORE_CFG_PCIE_CREDIT

PCI Express transmit completion header and data credit metering configuration.

BRIDGE_CORE_CFG_AXI_M_W_TICK_COUNT

AXI master write completion timeout configuration.

BRIDGE_CORE_CFG_AXI_M_R_TICK_COUNT

AXI master read completion timeout configuration.

BRIDGE_CORE_CFG_CRS_RPL_TICK_COUNT

PCIe configuration write/read request CRS replay timeout configuration.

E_BREG_CAPABILITIES

Egress bridge register translation: capabilities.

E_BREG_STATUS

Egress bridge register translation: status.

E_BREG_CONTROL

Egress bridge register translation: control.

E_BREG_BASE_LO

Egress bridge register translation: source address Low.

E_BREG_BASE_HI

Egress bridge register translation: source address High.

E_ECAM_CAPABILITIES

Egress ECAM translation: capabilities.

E_ECAM_STATUS

Egress ECAM translation: status.

E_ECAM_CONTROL

Egress ECAM translation: control.

E_ECAM_BASE_LO

Egress ECAM translation: source address Low.

E_ECAM_BASE_HI

Egress ECAM translation: source address High.

E_MSXT_CAPABILITIES

Egress MSI-X table translation: capabilities.

E_MSXT_STATUS

Egress MSI-X table translation: status.

E_MSXT_CONTROL

Egress MSI-X table translation: control.

E_MSXT_BASE_LO

Egress MSI-X table translation: source address Low.

E_MSXT_BASE_HI

Egress MSI-X table translation: source address High.

E_MSXP_CAPABILITIES

Egress MSI-X PBA translation: capabilities.

E_MSXP_STATUS

Egress MSI-X PBA translation: status.

E_MSXP_CONTROL

Egress MSI-X PBA translation: control.

E_MSXP_BASE_LO

Egress MSI-X PBA translation: source address Low.

E_MSXP_BASE_HI

Egress MSI-X PBA translation: source address High.

E_DREG_CAPABILITIES

Egress DMA register translation: capabilities.

E_DREG_STATUS

Egress DMA register translation: status.

E_DREG_CONTROL

Egress DMA register translation: control.

E_DREG_BASE_LO

Egress DMA register translation: source address Low.

E_DREG_BASE_HI

Egress DMA register translation: source address High.

E_ESUB_CAPABILITIES

Egress subtractive decode translation: capabilities.

E_ESUB_STATUS

Egress subtractive decode translation: status.

E_ESUB_CONTROL

Egress subtractive decode translation: control.

I_MSII_CAPABILITIES

Ingress PCI Express received MSI interrupt translation: capabilities.

I_MSII_CONTROL

Ingress PCI Express received MSI interrupt translation: control.

I_MSII_BASE_LO

Ingress PCI Express received MSI interrupt translation: source address Low.

I_MSII_BASE_HI

Ingress PCI Express received MSI interrupt translation: source address High.

I_MSIX_CAPABILITIES

Ingress PCI Express received MSI-X interrupt translation: capabilities.

I_MSIX_CONTROL

Ingress PCI Express received MSI-X interrupt translation: control.

I_MSIX_BASE_LO

Ingress PCI Express received MSI-X interrupt translation: source address Low.

I_MSIX_BASE_HI

Ingress PCI Express received MSI-X interrupt translation: source address High.

I_ISUB_CAPABILITIES

Ingress subtractive decode translation: capabilities.

I_ISUB_STATUS

Ingress subtractive decode translation: status.

I_ISUB_CONTROL

Ingress subtractive decode translation: control.

MSGF_MISC_STATUS

Received interrupt and message controller: miscellaneous interrupt status.

MSGF_MISC_MASK

Received interrupt and message controller: miscellaneous interrupt mask.

MSGF_MISC_SLAVE_ID

Slave error AXI ID.

MSGF_MISC_MASTER_ID

Master error AXI ID.

MSGF_MISC_INGRESS_ID

Ingress error AXI ID.

MSGF_MISC_EGRESS_ID

Egress error AXI ID.

MSGF_LEG_STATUS

Legacy interrupt status.

MSGF_LEG_MASK

Legacy interrupt mask.

MSGF_MSI_STATUS_LO

MSI interrupt status.

MSGF_MSI_STATUS_HI

MSI interrupt status.

MSGF_MSI_MASK_LO

MSI interrupt mask.

MSGF_MSI_MASK_HI

MSI interrupt mask.

MSGF_DMA_STATUS

DMA interrupt status.

MSGF_DMA_MASK

DMA interrupt mask.

MSGF_RX_FIFO_LEVEL

Received interrupt and message FIFO: level.

MSGF_RX_FIFO_POP

Received interrupt and message FIFO: pop element.

MSGF_RX_FIFO_TYPE

Received interrupt and message FIFO: message/interrupt type.

MSGF_RX_FIFO_MSG

Received message header.

MSGF_RX_FIFO_ADDRESS_LO

Received message/interrupt address.

MSGF_RX_FIFO_ADDRESS_HI

Received message/interrupt address.

MSGF_RX_FIFO_DATA

Received message/interrupt data payload.

TX_PCIE_IO_EXECUTE

PCIe I/O write/read request execution.

TX_PCIE_MSG_EXECUTE

PCIe message request execution.

TX_PCIE_MSG_CONTROL

PCIe message request execution: control.

TX_PCIE_MSG_SPECIFIC_LO

PCIe message request execution: message specific.

TX_PCIE_MSG_SPECIFIC_HI

PCIe message request execution: message specific.

TX_PCIE_MSG_DATA

PCIe message request execution: message data payload.