Bridge Initialization

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Bridge initialization is performed by the software driver running on the PS processor.

Note:   When using 32-bit addressing mode, Xilinx recommends using 256 MB space for PCIe (starting at address 0xE000_0000). For Root Port, 16 MB of this space can be used for ECAM and the rest of the 240 MB can be used for BARs for Endpoints.
If you require more than 256 MB space for PCIe, then use a higher addressing mode (40-bit or 44-bit).

1.Program the registers in the AXI-PCIe bridge with the following information.

Note:   After power on, these registers can be accessed using address 0xFD0E_0000 as documented in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4]. Access to registers is possible only by using the respective aperture addresses programmed after completing the bridge initialization and enabling the bridge translation.

2.Setup the AXI-PCIe bridge register apertures for bridge internal registers, ECAM aperture, and DMA register access.

a.Map the bridge register aperture.

AXIPCIE_MAIN.E_BREG_CONTROL[breg_size] = 4KB - 32KB
AXIPCIE_MAIN.E_BREG_BASE_LO = 0xFD0E0000
AXIPCIE_MAIN.E_BREG_BASE_HI = 0x00000000

b.Map the ECAM space.

AXIPCIE_MAIN.E_ECAM_CONTROL[ecam_size] = 4 KB (when Endpoint); 16 MB (when Root Port)
AXIPCIE_MAIN.E_ECAM_BASE_LO = 0xE0000000
AXIPCIE_MAIN.E_ECAM_BASE_HI = 0x00000000
AXIPCIE_MAIN.E_ECAM_CONTROL[ecam_enable] = 1

Note:   In the Root Port mode, this address can also be mapped to 40/44-bit space based on your requirement. In such cases care should be taken to program both ECAM_BASE_HI and ECAM_BASE_LO addresses appropriately.

c.Map DMA register aperture

AXIPCIE_MAIN.E_DREG_CONTROL[dma_size] = 0B
AXIPCIE_MAIN.E_DREG_BASE_LO = 0xFD0F0000
AXIPCIE_MAIN.E_DREG_BASE_HI = 0x00000000

Note:   Enable DMA register access, if Endpoint application is going to exercise DMA AXIPCIE_MAIN.E_DREG_CONTROL[dma_enable] = 1 (only for Endpoint mode).

3.For the Root Port mode.

a.Setup ingress MSI aperture.

AXIPCIE_MAIN.I_MSII_BASE_LO = 0xFE440000
AXIPCIE_MAIN.I_MSII_CONTROL[i_msii_enable] = 1

Note:   An address assigned by the software driver can also be used.

b.Disable DMA register access from Endpoint as there is no BAR in Root mapped to local registers.

AXIPCIE_MAIN.BRIDGE_CORE_CFG_PCIE_RX0[cfg_dma_reg_bar] = 7 (disabled)
AXIPCIE_MAIN.BRIDGE_CORE_CFG_PCIE_RX0[cfg_disable_pcie_dma_reg_access] = 1

c.Allow all upstream transactions (memory read, write) to access the AXI interface without any translation by enabling ingress subtractive decode.

AXIPCIE_MAIN.I_ISUB_CONTROL = 0x01

4.Enable translation apertures in the bridge for access by the AXI processor (i.e., after this access to bridge registers, the access is possible only by the use of the address programmed in AXIPCIE_MAIN.{E_BREG_BASE_HI, E_BREG_BASE_LO} and the DMA registers can be accessed by use of address programmed in AXIPCIE_MAIN.{E_DREG_BASE_HI, E_DREG_BASE_LO} and so on.

AXIPCIE_MAIN.E_BREG_CONTROL[breg_enable] = 1
AXIPCIE_MAIN.E_BREG_CONTROL[breg_enable_force] = 0

5.If using the Root Port mode, release pcie_reset_n from the MIO/GPIO programming registers. For Endpoint mode, wait for pcie_reset_n to be released by the host.

After the release of reset, link training is done with the peer and a link is established.

In the Endpoint mode, the host programs the PCIe configuration space registers inside the integrated block for PCIe.