The digital CDR loop filter takes in the main recovered clock and the four data samples from the IQ samplers and generates the IQ PI codes as output. This loop filter, in combination with the samplers and PI, forms a proportional and integral negative feedback loop to align the I phase of the recovered clock to the center point of the received data bits. The deserializer converts the half-rate data from the samplers to 10-bit symbol data, which is then given to the receiver control module for further processing before it is passed to the PCS.
The PI controller converts the output PI codes from the CDRLF to thermometric format as accepted by the analog PI. The CDRLF, deserializer, and PI controller constitute a digital module that is synthesized and implemented using the digital flow tools. This block runs at a clock speed of 3 GHz.