CPU Debug

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

An input cpu_debug is provided by the SWDT. It is possible to stop the CPU and analyze the content of system register and memory. To enable diagnosis of system problems during prototype commissioning, connect the signal that stops the CPU to the SWDT input cpu_debug. This suspends the SWDT and it will not time out on a CPU that is stopped for diagnostic purposes.