CPU Private Peripheral Interrupts

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The functionality of the RPU PPIs are described by the GICv1 architecture specification. This is a subset of the APU PPI functionality that is described by the GICv2 specification.

Each CPU connects to a private set of peripheral interrupts. The list for the RPU is a subset of the APU. The sensitivity type (edge or level) for PPIs are fixed and cannot be changed.