CRC Field

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The CRC is calculated using a 128-bit sum. This field is only valid if EN_CRC_CHK is set. Software generates the CRC and stores it, along with DSCR. When the CRC check is enabled, the DPDMA uses the CRC field to verify the data integrity. To calculate the CRC, the following steps are used.

1.Initialize CRC descriptor field to zero.

2.The descriptor size is 512 bits. The CRC is calculated using 32-bit addition of 16, 32-bit words.

3.Any carry generated during an addition is not used.

4.CRC = word[0] + word[1] + ... + word[15].

The received descriptor is checked against the CRC using following scheme.

1.Calculated CRC = word[0] + word[1] + ... + word[14].

2.Word[15] == calculated CRC.

The DSCR registers reflect the current states from hardware. When the DMA channel is running these multiple registers keep updating (some of these might have partial updates), whereas some registers may still hold the previous status. In order to avoid partial reads:

1.The channel can be paused and read, however, this is not reasonable as it takes time to pause and it disturbs the current streaming.

2.The channel can be read at specific timing. Once a new descriptor is scheduled there’s an interrupt (sync) and the DMA channel operates on the descriptor. The descriptor states stay the same for that period and they can be read in the beginning of the period upon the interrupt. It’s unlikely to read partially, but the inner descriptor states such as current payload address will keep on changing within a descriptor period.