CRF APB Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The CRF_APB write-protected registers are listed Table: Write-protected Registers, CRF_APB. The protection is controlled by the CRF_APB.CRF_WPROT [active] bit.

Table 16-15:      Write-protected Registers, CRF_APB

Registers

Count

Registers

Count

Registers

Count

acpu_ctrl

1

dll_ref_ctrl

1

qspi_ref_ctrl

1

adma_ref_ctrl (LPD_DMA)

1

dp_audio_ref_ctrl

1

reset_ctrl

1

ams_ref_ctrl

1

dp_stc_ref_ctrl

1

reset_reason

1

apll_{cfg,ctrl}

2

dp_video_ref_ctrl

1

rpll_{cfg,ctrl}

2

apll_frac_cfg

1

dpll_cfg

1

rpll_frac_cfg

1

apll_to_lpd_ctrl

1

dpll_frac_cfg

1

rpll_to_fpd_ctrl

1

bank3_ctrl{0:5}

6

dpll_to_lpd_ctrl

1

rst_ddr_ss

1

bank3_status

1

gdma_ref_ctrl (FPD_DMA)

1

rst_fpd_apu

1

blockonly_rst

1

gem_tsu_ref_ctrl

1

rst_fpd_top

1

boot_mode_{por,user}

2

gem{0:3}_ref_ctrl

4

rst_lpd_dbg

1

can{0,1}_ref_ctrl

2

gpu_ref_ctrl

1

rst_lpd_iou{0,2}

2

chkr{0:7}_clka_lower

8

i2c{0,1}_ref_ctrl

2

rst_lpd_top

1

chkr{0:7}_clka_upper

8

acpu_ctrl

1

sata_ref_ctrl

1

chkr{0:7}_clkb_cnt

8

iopll_{cfg,ctrl}

2

sdio{0,1}_ref_ctrl

2

chkr{0:7}_ctrl

8

iopll_frac_cfg

1

spi{0,1}_ref_ctrl

2

clkmon_{disable,enable}

2

iopll_to_fpd_ctrl

1

timestamp_ref_ctrl

1

clkmon_{mask,status}

2

iou_switch_ctrl

1

topsw_lsbus_ctrl

1

clkmon_trigger

1

lpd_lsbus_ctrl

1

topsw_main_ctrl

1

cpu_r5_ctrl

1

lpd_switch_ctrl

1

uart{0,1}_ref_ctrl

2

csu_pll_ctrl

1

nand_ref_ctrl

1

usb{0,1}_bus_ref_ctrl

2

dbg_fpd_ctrl

1

pcap_ctrl

1

usb3_dual_ref_ctrl

1

dbg_lpd_ctrl

1

pcie_ref_ctrl

1

vpll_{cfg,ctrl}

2

dbg_trace_ctrl

1

pl{0:3}_ref_ctrl

4

vpll_frac_cfg

1

dbg_tstmp_ctrl

1

pl{0:3}_thr_ctrl

4

vpll_to_lpd_ctrl

1

ddr_ctrl

1

pll_status

1