CSU BootROM Error Codes

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Any error from the CSU while in the boot process is recorded in the PMU_GLOBAL.CSU_BR_ERR register. This register also determines the boot success or failure. On failure or error condition, the 16-bit error code is recorded in the CSU_BR_ERR register.

A configuration BootROM error code is 8 bits long. This means that with an allocation of 16 bits, two error codes are stored. Error bits [15-8] correspond to the first image error code and error bits [7-0] indicate the most recent image error code (Table: BootROM Error Bits).

Table: BootROM Error Bits describes the configuration BootROM(CBR) error codes.

Table 11-8:      BootROM Error Bits

15

 

 

 

 

 

 

8

7

 

 

 

 

 

 

0

First Image Error

Last Image Error

Table: BootROM Error Codes describes the configuration bootRAM (CBR) error codes.

Table 11-9:      BootROM Error Codes

Error Code

Description

Solution

0x10

Secure processor voting has failed during boot.

Ensure LPD power supply is correct and power on reset (POR) the chip.

0x11

Secure processor is unable to power up the OCM.

Ensure LPD power supply is correct and POR the chip.

0x12

An error occurred while initializing the OCM with 0xDEADBEEF value.

Ensure LPD power supply is correct and POR the chip.

0x14

eFUSE is not properly loaded by hardware. There is a parity error in eFUSE values.

Ensure LPD power supply is correct and (POR) the chip.

0x15

The TBITs in eFUSE are not properly written. For a successful boot, TBITS in eFUSE should have either all zeros or a 1010b pattern.

Check the TBITS values and POR the chip.

0x16

DMA transfer timeout error during the OCM initialization.

Ensure LPD power supply is correct and (POR) the chip.

0x17

eFUSE controller is unable to load the eFUSE values to the cache registers.

Ensure LPD power supply is correct and (POR) the chip.

0x20

eFUSE RSA bits read from eFUSE has a mismatch.

 

0x23(1)

Error occurred during QSPI 24 boot mode initialization.

Check that the Quad-SPI device is properly connected to the QSPI MIO pins.

Ensure the width detection word is set equal to the data pattern 0xAA995566 and that the image identification word has x584C4E58, 'XLNX'.

Ensure that the device content is not blank in single device applications.

0x24

Error occurred during QSPI 32 boot mode initialization.

Check that the Quad-SPI device is properly connected to the QSPI MIO pins.

Ensure the width detection word is set equal to the data pattern 0xAA995566 and that the image identification word has x584C4E58, 'XLNX'.

Ensure that the device content is not blank.

0x25

Error occurred during NAND boot mode initialization.

Check that the NAND device is properly connected to the NAND MIO pins.

Ensure the width detection word is set equal to the data pattern 0xAA995566 and that the image identification word has x584C4E58, 'XLNX'.

Ensure that the device content is not blank.

0x26

Error occurred during SD boot mode initialization.

Check that the SD device is properly connected to the SD MIO pins.

Ensure SD card is formatted properly with FAT32/FAT16 file system.

0x27

Error occurred during eMMC boot mode initialization.

Check that the eMMC device is properly connected to the eMMC MIO pins.

Ensure that the MMC card is formatted properly with the FAT32/FAT16 file system.

0x2A

Invalid boot mode is selected in the boot mode setting.

Ensure the boot mode pins values are valid.

0x30

Boot header does not have an XLNX string.

Ensure that the Image Identification word has x584C4E58, 'XLNX' in the Boot header.

0x31

Boot header checksum is wrong or boot header fields are not length aligned.

Ensure that the boot header checksum is correctly calculated and written to flash device. Also, ensure all the length fields are word aligned.

0x32

Boot header encryption status value is not valid. Key selected is not a valid key source.

Ensure that the key source value in Encryption Status field is valid.

0x33

Boot header attributes value is not valid. Reserved fields in image attributes are not zero.

Ensure that the reserved field is ZERO in the Image attributes.

0x34

Either of the boot header PMU firmware length and total PMU firmware length fields are not valid.

Ensure the PMU firmware length fields are in valid range.

Ensure PMU firmware length is more than the total PMU firmware length.

0x35

Either of the boot header FSBL and total FSBL length fields are not valid.

Ensure the FSBL length fields are in valid range.

Ensure the FSBL length is more than the total FSBL length.

0x36

Selected does not support the XIP mode.

Ensure the boot mode pins are set QSPI.

Only non-secure images are allowed in XIP mode. Ensure image is secure.

0x37

FSBL execution address is not in the OCM address range.

Ensure the FSBL execution address in the OCM 256K region.

0x38

Source offset is not valid. It is beyond the flash image search limit.

Check if the offset in the flash is beyond the flash image search limit. The offset is calculated from the multi boot register value and source offset field in boot header.

0x3A

Authentication only is selected, but no key source is selected (for selecting the device key source) or authentication only is selected, but no authentication is selected in eFUSE or the boot header.

To use the authentication only feature, the encryption key shall be selected so that ROM can unlock that key. Authentication of the image is mandatory. Enable eFUSE or boot header authentication.

0x3B

Reading failed from the selected boot device.

Ensure the boot device is properly connected and right boot mode is selected.

0x3D

Selected CPU is disabled in the eFUSE.

Ensure A53 CPU is enabled for the chip when A53-0 is selected as a hand off CPU.

0x3E

Time out occurred while calculating the PPK hash.

Ensure power supply are proper and POR the chip.

0x3F(2)

Boot with boot header helper data is not allowed until eFUSE helper data is invalidated.

To use the PUF helper data it is necessary to set the SYN_INVALID bit in eFUSE.

0x40

Boot header and eFUSE RSA are enabled at the same time, which is not allowed.

The boot header and eFUSE RSA should not be enabled at the same time. Ensure the RSA eFUSE is not blown when boot header RSA is selected.

0x41

Selected PPK value in boot header is not valid.

ROM supports 2 PPK keys. Ensure the proper key value is used in the Boot header.

0x42

Selected PPK is revoked.

Ensure the selected PPK is not revoked in eFUSE.

0x43

All PPK in the device are revoked.

All PPK present inside the chip are revoked. Authentication cannot be performed on this chip.

0x44

Mismatch in the PPK hash calculated from Boot header and PPK hash in eFUSE

Ensure the correct PPK is burned inside the eFUSEs.

Ensure the PPK keys used to create boot image match the RSA public key that is present inside the chip.

0x45

SPK signature verification is failed

Ensure the SPK signature is created with the PPK that is present in the authentication certificate.

Ensure the SPK ID present in the boot header is same as eFUSE SPK ID.

0x46

Selected SPK ID is not matching with the eFUSE SPK ID.

Ensure the SPK ID present in the boot header is same as the eFUSE SPK ID.

0x47

Boot header signature is failed.

Ensure the boot header signature is created with the SPK that is present in the authentication certificate.

0x48

Selected boot mode does not support the golden image search.

Golden Image search is supported only by QSPI, NAND, and SD boot modes. For all other boot modes, the multi boot register value should be zero.

0x49

No image found in QSPI after searching the allowed address range.

ROM reached end of the image search limit for a QSPI device and no other good image is found.

Ensure image in the QSPI is valid.

0x4A

No image found in NAND after searching the allowed address range.

ROM reached end of the image search limit for a NAND device and no other good image is found.

Ensure the image in the NAND is valid.

0x4B

No image found in the SD/eMMC after searching the allowed number of files.

ROM reached end of the file limit for a SD/eMMC device and no other good image is found.

Ensure the boot file is valid in the SD/eMMC FAT file system.

0x4D

Time out error while calculating the SPK SHA hash.

Ensure the LPD power supply is correct and POR the chip.

0x4E

Time out error while calculating the boot header SHA hash.

Ensure the LPD power supply is correct and POR the chip.

0x50

Mismatch while writing to the secure registers.

Ensure the LPD power supply is correct and POR the chip.

0x51

Changing the state of the device from secure to non-secure is not allowed.

After POR, if first image is secure then subsequent images are secure.

0x52

Changing the key source is not allowed while in the secure state.

Ensure the key source is the same across multiple images used for boot in POR and SRST.

0x53

Changing the state from non-secure to secure is not allowed.

Ensure the key source is the same across multiple images used for boot in POR and SRST.

0x54

BBRAM key is disabled in eFUSE but the key source selected is BBRAM.

Ensure the BBRAM_DIS eFUSE bit is not set when BBRAM is selected as a key source.

0x55

Only encrypted boots with the eFUSE key source are allowed.

When ENC_ONLY eFUSE bit is set, no other key sources are allowed apart from eFUSE.

0x60

One of the register addresses in the boot header is not allowed.

Ensure the register addresses in the boot header are in the valid address range allowed by ROM.

0x61

Copying from selected boot device failed after register initialization.

Ensure the frequencies or any modifications done to boot devices through register initialization are correct.

0x62

Boot header read after register initialization is mismatched with the original boot header.

Ensure the frequencies or any modifications done to boot devices through register initialization are correct. Data read after register initialization does not match the previous values.

0x70

Error occurred while copying the PMU FW.

Ensure the boot device is connected correctly.

Ensure the frequencies or any modifications done to boot devices through register initialization are correct.

0x71

Error occurred while copying the FSBL.

Ensure the boot device is connected correctly.

Ensure the frequencies or any modifications done to boot devices through register initialization are correct.

0x72

Time out occurred while loading the key.

Ensure LPD power supply is correct and POR the chip.

0x73

Time out occurred while using the CSU DMA in image processing for AES/SHA.

Ensure LPD power supply is correct and POR the chip.

0x74

Time out occurred for the PMU to go to sleep.

 

0x75

Time out occurred while calculating the SHA during boot image signature verification.

Ensure LPD power supply is correct and POR the chip.

0x76

Time out occurred while calculating the SHA for boot image during the integrity check.

Ensure LPD power supply is correct and POR the chip.

0x78

Boot image signature mismatch occurred.

Ensure the boot image signature is created with the SPK that is present in authentication certificate.

0x79

Error occurred while decrypting the PMU firmware.

Ensure same keys are used as present in the chip for encrypting the Boot image.

Ensure the right key source is used for encrypting the image.

0x7A

Error occurred while decrypting the FSBL.

Ensure the same keys are used as present in the chip for encrypting the Boot image.

Ensure right key source is used for encrypting the image.

0x7B

Mismatch in the hash while checking for the boot image integrity.

Ensure the SHA3 is used while creating the boot image integrity.

0x80

Unable to power up the selected CPU.

Ensure the power rail is ON for the selected CPU. FPD in case of A53.

0x81

Unable to wake up the PMU after loading the PMU firmware.

Ensure the PMU Firmware is running properly and set FW_IS_PRESENT bit after completing initialization.

0x90

Tamper event that is detected while in post boot. Every tamper event is stored in an error register with 0x90 + Index. Index is the tamper event ID according to the CSU tamper register.

This is tamper detection by ROM during post boot.

Ensure all voltages are in range.

Ensure JTAG is not toggled when it is disabled.

0xA0

Error when selected boot mode does not support fallback.

Ensure no error is present in the first image during USB boot mode.

0xB0

Error when exceptions occurs while booting.

Ensure the LPD power supply is proper and POR the chip.

0xB1

Error when exceptions occurs while in post boot.

Ensure the LPD power supply is proper and POR the chip.

Notes:

1.To use QSPI32 boot mode for flash sizes greater than 16 MB.

2.Once the SYN_INVALID bit is set in eFUSE, the system does not allow to boot with eFUSE PUF helper data.