CSU DMA

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The CSU DMA allows the CSU to move data efficiently between the memory and the CSU stream peripherals (AES, SHA, PCAP), using the secure stream switch. The CSU DMA can access the OCM, TCM, and DDR memory. The CSU DMA is a two-channel, simple DMA, allowing separate control of the SRC (read) channel and DST (write) channel with a 128 x 32-bit data FIFO for each channel. The DMA is effectively able to transfer data.

From the PS-side to the secure stream switch (SSS) side (SRC DMA only).

From the SSS-side to the PS-side (DST DMA only).

Simultaneously from the PS-side to the SSS-side and from the SSS-side to the PS-side.

The APB interface allows for control and monitoring of the CSU DMA module’s functions. A single interrupt output port is sent to the CSU. It is combined with other interrupt sources before being sent out to the interrupt controller on a single interrupt pin.

Two clocks are provided, one for the main CSU DMA operation and one for the APB interface. Along with these clocks, there are two-reset inputs. These reset pins are synchronized to the respective clock domains by the CSU before sending them to the CSU DMA.

The DMA interfaces with a secure-stream switch through two sets of handshake signals; one for the DMA SRC (memory to stream) direction and the other for the DMA DST (stream-to-memory) direction.

The DMA has a DST_FIFO that is sized to hold a minimum of one PL configuration frame. Although overflow is not anticipated, an interrupt register (FIFO_OVERFLOW) is provided in cases where an overflow occurs.