CSU Resets

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The different secure blocks of the CSU are reset by writing to the registers in Table: CSU Reset Registers. Write 1 to assert reset, write 0 to deassert reset.

Table 12-1:      CSU Reset Registers

Component

Reset Register Name

AES-GCM

aes_reset

PCAP

pcap_reset

SHA-3/384

sha_reset