Cache Coherent Interconnect

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The cache-coherent interconnect (CCI) combines parts of the interconnect and coherency functions into a single block. It provides two ACE slave ports (for full coherency), three ACE-Lite slaves (for I/O coherency), two ACE-Lite master ports (for DDR), and one ACE-Lite master port for non-DDR memory-mapped accesses. It also provides the distributed virtual memory (DVM) message interface to the system memory management unit (SMMU). This Figure shows the CCI port connections. CCI registers are globally mapped and can be accessed from the LPD.