Cache Protection

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The Cortex-A53 MPCore processor supports cache protection in the form of ECC on RAM instances in the processor using two separate protection options.

SCU-L2 cache protection

CPU cache protection

These options enable the Cortex-A53 MPCore processor to detect and correct a one-bit error in any RAM and detect two-bit errors in some RAMs.

Cortex-A53 MPCore RAMs are protected against single-event-upset (SEU) such that the processor system can detect and continue making progress without data corruption. Some RAMs have parity single-error detect (SED) capability, while others have ECC single-error correct, double-error detect (SECDED) capability.

Note:   The L1 instruction cache is protected by parity bits. It does not implement error correction code.

The processor can make progress and remain functionally correct when there is a single-bit error in any RAM. If there are multiple single-bit errors in more than one RAM, or within different protection granules within the same RAM, then the processor also remains functionally correct. If there is a double-bit error in a single RAM within the same protection granule, then the behavior depends on the RAM.

For RAMs with ECC capability, the error is detected and reported if the error is in a cache line containing dirty data.

For RAMs with only parity, a double-bit error is not detected and therefore, could cause data corruption.

Interrupts upon an error event allow for the system to take the proper action, including flushing and re-loading caches, logging the error, etc. Multi-bit upsets (MBU) are avoided by proper interleaving, choice of ECC, and parity coding.