Card to System Flow (EP Memory to Host Memory)

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Host software sets up and manages the DST and STAD Q elements in host memory; Arm software (driver on the Zynq UltraScale+ MPSoC) sets up and manages the SRC and STAS Q elements in AXI memory.

2.The source buffer lies in the AXI memory and destination buffer in PCIe memory.

3.DMA channel's registers are programmed by both host CPU and AXI CPU. Registers corresponding to SRC/STAS Qs by the AXI CPU, and DST/STAD Qs by the host.

4.On DMA channel enable, SRC elements are fetched over AXI (read transactions) and DST elements over PCIe.

5.The source buffer pointed by SRC-Q is fetched over AXI (read transaction) and made available to the destination address (provided by DST-Q) as memory write TLP over PCIe.

6.On completion of the operation, the STAS-Q is updated in AXI memory and the STAD-Q is updated in host memory.