Change Timing Mode for SDR and NV-DDR

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Table 25-13:      Change Timing Mode for SDR and NV-DDR

Task

Register

Register Field

Register Offset

Bits

Value (Binary)

If the interface is NV-DDR, program the ONFI set feature with the data interface and timing values for all targets.

If the interface is SDR:

Change clock frequency with SDR CLK 100 MHz.

Update the new data interface and timing mode values in the data interface register.

Reset all targets (refer to Reset the Target Device (ONFI Reset))

Set feature with new modes (ONFI Set Feature)