Clearing Pending Interrupts from the APU GICv2

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The GICv2 gets reset based on reset of the interconnect and does not have a soft reset bit. These steps ensure that all pending interrupts are cleared after the CPU comes back up from a reset:

1.Write the value FFFF_FFFFh into the GICD_ICENABLERx register.

2.Write the value FFFF_FFFFh into the GICD_ICPENDRx   register.

3.Write the value FFFF_FFFFh into the GICD_ICACTIVERx register.

4.Write the value FFFF_FFFFh into the GICD_CPENDSGIRx register.

The following is sample FSBL code for clearing the pending interrupts from the APU GICv2.

XFsbl_Printf (DEBUG_GENERAL, "Clear pending interrupts from APU GIC\n\r");
for (i = 0; i < 6; i++) {

         Xil_Out32 (GICD_BASEADDR + 0x180 + 4*i, 0xffffffff); // GICD_ICENABLERx (x= 0 to 5)

         Xil_Out32 (GICD_BASEADDR + 0x280 + 4*i, 0xffffffff); // GICD_ICPENDRx (x= 0 to 5)

         Xil_Out32 (GICD_BASEADDR + 0x380 + 4*i, 0xffffffff); // GICD_ICACTIVERx (x= 0 to 5)

}

 

   for (i = 0; i < 4; i++) {

         Xil_Out32 (GICD_BASEADDR + 0xF10 + 4*i, 0xffffffff); // GICD_CPENDSGIRx (x= 0 to 3)

}