Clock Domains

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The gigabit Ethernet controller has the following clocks.

AXI clock: AXI clock used by DMA controller.

APB clock: APB clock used by MAC registers.

TSU clock: Alternate clock source for the time stamp unit (TSU).

TX clock (tx_clk): MAC transmit clock used by MAC transmit unit in MII/RGMII/GMII/SGMII, 1000BASE-SX, or 1000BASE-LX mode.

RX clock (rx_clk): MAC receive clock used by MAC receive synchronization in MII/RGMII/GMII/SGMII, 1000BASE-SX, or 1000BASE-LX mode.

Invert TX clock: Inverted TX clock used in loopback mode.

PCS transmit clock: In all modes except SGMII, 1000BASE-SX, and 1000BASE-LX, this clock can be sourced directly from tx_clk. In SGMII, 1000BASE-SX, or 1000BASE-LX applications, this clock is sourced from the serializer/deserializer and fixed at 125 MHz because the GEM PCS only operates at 1000 Mb/s.

RBC0/RBC1 clock: Used in the PCS receive channel.

The following restrictions apply when generating a reference clock for GEM.

Do not use fractional divisors in the PLL to generating the 125 MHz clock for the GEM module.

Any frequency variation should be within 100 PPM.