Clock Generator Programming Example

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This example shows the programming steps to enable an LPD main switch clock with the IOPLL clock and to divide the result by four.

1.Set CRL_APB.LPD_SWITCH_CTRL[CLKACT] = 1.

2.Set CRL_APB.LPD_SWITCH_CTRL[SRCSEL] = 010b.

3.Program divider by writing to CRL_APB.LPD_SWITCH_CTRL[DIVISOR0] = 04h.