The clock monitor measures the frequency of one clock using another clock as a reference. This monitor does not monitor duty cycle, jitter, or quality. The clock monitor uses a reference clock that counts for a predetermined number of cycles set by the control register. During that time, another counter in the second clock domain is counting. When the reference clock counter is done, the second clock domain is signaled to stop counting and then compares its count value to two pre-programmed registers. If the counted value is within the bounds of the registers, then the clock being measured is within tolerable parameters. If it is not, then an interrupt is provided to the interrupt controller.