Clock Monitor Programming Example

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This example shows the programming steps to program the clock monitors. The example assumes that the PS_REF_CLK is 50 MHz and the APB LPD bus clock (LPD_LSB_CLK) is 100 MHz. All registers are in the CRL_APB register set. The clock sources are listed with the definitions of the CHKRx_CTRL registers in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].

1.Program the clock sources:

Set CHKRx_CTRL [clka_mux_ctrl] = 011b  (LPD_LSBUS_CLK).

Set CHKRx_CTRL [clkb_mux_ctrl] = 0 (PS_REF_CLK).

2.Program the counter values:

Set CHKRx_CLKB_CNT [value] = 0000_0000h.

Set CHKRx_CLKA_UPPER [thrshld] = 0001_028Ah.

Set CHKRx_CLKA_LOWER [thrshld} = 0000_FD76h.

3.Prime the pump:

Set CHKRx_CTRL [enable] = 1.

4.Start the clock monitor:

Set CHKRx_CTRL [start_single] = 1.