A full-rate CMOS-level clock is distributed from the PLL module to the receiver. The PLL clock goes into the clock processor module. This module divides down the PLL full-rate clock as per the programmed division factor and provides two differential phases of this divided clock as output. Because the receiver front end operates at half rate, the division factor is always programmed to give two half-rate clocks. Thus, for a division factor of two, the outputs are 0° and 180° phases of a half-rate CMOS clock.