Clock, Reset, and Configuration Pins

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The clock pins include the main PS reference clock input and the clock crystal connections to the real-time clock (RTC) in the battery power domain. The reset and configuration pins control the device and provide status information.

Table 2-2:      Clock, Reset, and Configuration Pins

Pin Name

Direction

Type

Description

PS_REF_CLK

Input

Dedicated

System reference clock.

PS_PADI

Input

Dedicated

Crystal pad input (RTC).

PS_PADO

Output

Dedicated

Crystal pad output (RTC).

PS_POR_B

Input

Dedicated

Power-on reset signal.

POR_OVERRIDE

Input

Dedicated

POR delay override.
0 = Standard PL power-on delay time(1) (recommended default).

1= Faster PL power-on delay time.(1)

Do not allow this pin to float before and during configuration. This pin must be tied to VCCINT or GND.

PS_SRST_B

Input

Dedicated

System reset commonly used during debug.

PS_MODE

Input/Output

Dedicated

4-bit boot mode pins sampled on POR deassertion.

PS_INIT_B

Input/Output

Dedicated

Indicates the PL is initialized after a power-on reset (POR). This signal should not be held Low externally to delay the PL configuration sequence because the signal level is not visible to software. However, if there is a CRC error detected when the PL bitstream is loaded PS_INIT_B will be driven low.

PS_DONE

Output

Dedicated

Indicates the PL configuration is completed. Requires an external pull-up resistor.

PS_PROG_B

Input

Dedicated

PL configuration reset signal.

PS_ERROR_OUT

Output

Dedicated

Asserted for accidental loss of power, a hardware error, or an exception in the PMU.

PS_ERROR_STATUS

Output

Dedicated

Indicates a secure lockdown state. Alternatively, it can be used by the PMU firmware to indicate system status.

PS_MGTREFCLK[3:0]

Input

Dedicated

Reference clock for the PS-GTR transceivers.

PUDC_B

Input

Dedicated

Pull-Up During Configuration (bar) Dedicated input pin. Active-Low input enables internal pull-up resistors on the SelectIO pins after power-up and during configuration. When PUDC_B is Low, internal pull-up resistors are enabled on each SelectIO pin. When PUDC_B is High, internal pull-up resistors are disabled on each SelectIO pin. Caution! Do not allow this pin to float before and during configuration. Must be tied High or Low. PUDC_B must be tied either directly or via a ≤ 1 k Ω resistor to VCCAUX or GND.

1.The Tpor specification begins when the last of the monitored supplies (VCCINT, VCCAUX, VCCBRAM) reaches 95% of its recommended operating condition voltage.