Clock Scheme

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The controller for PCIe operates in multiple clock domains. This Figure shows the clock domains. The pipe_clk and user_clk are derived from the PS-GTR transceiver interface provided 250 MHz clock.

Figure 30-2:      Controller for PCIe Clock Domains

X-Ref Target - Figure 30-2

X15486-pcie-clk-scheme-block.jpg

Table: Clock Description provides a description of the clocks.

Table 30-1:      Clock Description

Clock

Description

PCIe 100 MHz reference clock

The PCIe protocol specifies a 100 MHz clock with spread spectrum. This clock is used as a reference clock to the PS-GTR transceiver interface, which is part of the PHY. The PS-GTR transceiver interface generates a 250 MHz clock from this reference clock for the parallel datapath. This clock comes from external interface (typically on-board clock source in the case of Root Port mode, and sourced by a host system via the PCIe slot in the case of Endpoint mode). Only common clock mode is supported for reference clock.

pipe_clk

The PS-GTR transceiver interface provided clock is converted to a 125 MHz clock for a Gen1 link and a 250 MHz clock for a Gen2 link.

user_clk

This is a 250 MHz clock derived from a PS-GTR transceiver interface provided clock. The link and transaction layers of the integrated block for PCIe operate in this clock domain. The AXI-PCIe bridge interfaces to the integrated block for PCIe in the user_clk domain.

apb_clk

The APB interface and its associated register block and supporting logic runs in the apb_clk domain. This clock domain is independent of all other domains in terms of frequency and phase and is derived from the PLL on the PS.

axi_clk

The AXI interfaces of the AXI-PCIe bridge run in the axi_clk domain. This domain is independent of all other domains in terms of frequency and phase. To keep up with the x4 Gen2 throughput requirements, this clock needs to be at least 250 MHz.

This clock is derived from the PLL on the PS and can be programmed to a lower frequency for lower performance PCIe configurations through the CRF_APB.PCIE_REF_CNTRL registers. For non-x4 Gen2 configurations, the 125 MHz is sufficient to achieve the best performance.