Clock Source Programming Example

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The programming steps to use video_ref_clk as the clock source for IOPLL are used in this example.

1.Program the PLL into bypass by setting IOPLL_CTRL[BYPASS] = 1.

2.Assert the reset to IOPLL by setting IOPLL_CTRL[RESET] = 1.

3.Set IOPLL_CTRL[PRE_SRC] = 100b, the VIDEO_REF_CLK.

4.Deassert the IOPLL reset by configuring IOPLL_CTRL[RESET] = 0.

5.Check for PLL lock by checking PLL_STATUS[IOPLL_LOCK] = 1.

6.Disable bypass mode by setting IOPLL_CTRL[BYPASS] = 0.

 

IMPORTANT:   The following clocks should never be made inactive: LPD_SWITCH_CLK, LPD_LSB_CLK, TOPSW_MAIN_CLK, and TOPSW_LSBUS_CLK. Whenever changing a CLK source, ensure that any downstream clocks are prevented from exceeding their maximum clock frequency.