Clock System Overview

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PS subsystem clock unit has five PLL clock units and many clock generators for system elements. The landscape of the system clock units are represented in This Figure. Clock generators have either one or two programmable divider units. Some clock generators have more than one clock-active control. The RTC and PMU have standalone clock generators.

Figure 37-1:      System Clocks Block Diagram

X-Ref Target - Figure 37-1

X19873-ps-clocks-block-diagram.jpg