Clocking Overview

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The SD clock generator generates the SD clock from the reference clock (sdio_ref_clk) based on the controls programmed in the clock control register (SDIO.reg_clockcontrol). These include the clock divide value, SD clock enable, etc. The outputs are the SD_CLK and the SD_CARD clock. The SD_CLK is used by the most of the SD control logic (SD Command Control, SD transmit control, SD tuning block and block buffer). The SD_CARD clock is the same as SD_CLK, except that this is available only when the SD clock enable (SDIO.reg_clockcontrol [clkctrl_sdclkena]) bit is set and is connected to the SD_CLK pin on the SD interface. This Figure shows the clocking architecture.

Figure 26-3:      Clocking Architecture

X-Ref Target - Figure 26-3

X19890-sd-clock-generator.jpg

The host controller supports both full speed and high speed cards. For the high speed card, the host controller should clock out the data at the rising edge of the SDIO clock. For the full speed card, the host controller should clock out the data at the falling edge of the SDIO clock.

The host bus interface (AXI Master/Slave), the host control register set, and the PIO/DMA controller operate on the AXI interface clock.