Clocks

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The SPI controller receives two clock inputs from the PS clock subsystem and, in slave mode, the SCLK clock from the attached SPI master.

SPI_REF_CLK clock operates the controller and the baud-rate divider for the SCLK in master mode.

LPD_LSBUS_CLK clock operates the APB slave interface for register access. Refer to Answer Record 73356.

These clocks run asynchronous to each other. Clock generation is described in PS Clock Subsystem. The clock frequency specifications are defined in the data sheet.