Commanded I2C Transactions

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The controller supports a special AUX channel command intended to make I2C over AUX transactions faster and easier to perform. In this case, the host bypasses the external I2C master/slave interface and initiates the command by directly writing to the register set. The sequence for performing these transactions is exactly the same as a native AUX channel transaction with a change to the command written to the AUX_COMMAND register. The supported I2C commands are summarized in Table: I2C Commands.

Table 33-20:      I2C Commands

Aux_Command[11:8]

Command

0x0

I2C write

0x4

I2C write middle of transaction (MOT)

0x1

I2C read

0x5

I2C read MOT

0x6

I2C write status with MOT

0x2

I2C write status

By using a combination of these commands, the host can emulate an I2C transaction. The flow of commanded I2C transactions is shown in This Figure.

Figure 33-22:      Commanded I2C Transactions

X-Ref Target - Figure 33-22

X15512-i2c-flow.jpg

Because I2C transactions can be significantly slower than AUX channel transactions, the host should be prepared to receive multiple AUX_DEFER reply codes during the execution of the state machines.

The AUX-I2C commands are as follows.

MOT definition.

°Middle of transaction bit in the command field.

°This controls the stop condition on the I2C slave.

°For a transaction with MOT set to 1, the I2C bus is not stopped, but left to remain in the previous state.

°For a transaction with MOT set to 0, the I2C bus is forced to idle at the end of the current command or in special abort cases.

Partial ACK.

°For I2C write transactions, the sink controller can respond with a partial ACK (ACK response followed by the number of bytes written to I2C slave).

Special AUX commands include the following.

Write address only and read address only commands do not have any length field transmitted over the AUX channel. The intent of these commands are as follows.

°Send address and RD/WR information to I2C slave. No data is transferred.

°End previously active transaction, either normally or through an abort.

The address-only write and read commands are generated from the source by using bit [12] of the command register with command as I2C WRITE/READ.

The write status command does not have any length information. The intent of the command is to identify the number of bytes of data that have been written to an I2C slave when a partial ACK or defer response is received by the source on a AUX-I2C write. The write status command is generated from the source by using bit [12] of the command register with command as I2C WRITE STATUS.

The generation of AUX transactions is described in Table: AUX Transactions.

Table 33-21:      AUX Transactions

Transaction

AUX Transaction

IIC Transaction

Usage

Sequence

Write address only with MOT = 1.

START ->

CMD ->

ADDRESS ->

STOP

START ->

DEVICE_ADDR ->

WR ->

ACK/NACK

Setup I2C slave for write to address defined.

Write AUX address register (0x108) with device address.

Issue command to transmit transaction by writing into AUX command register (0x100).

Bit [12] must be set to 1.

Read address only with MOT = 1.

START ->

CMD ->

ADDRESS ->

STOP

START ->

DEVICE_ADDR ->

RD ->

ACK/NACK

Setup I2C slave for read to address defined.

Write AUX address register with device address.

Issue command to transmit transaction by writing into AUX command register.

Bit [12] must be set to 1.

Write/Read address only with MOT = 0.

START ->

ADDRESS ->

STOP

STOP

To stop the I2C slave, used as abort or normal stop.

Write AUX address register (0x108) with device address.

Issue command to transmit transaction by writing into AUX command register (0x100).

Bit [12] must be set to 1.

Write with MOT = 1.

START ->

CMD ->

ADDRESS ->

LENGTH ->

D0 to DN ->

STOP

I2C bus is IDLE or new device address.

START ->

START/RS ->

DEVICE_ADDR ->

WR ->

ACK/NACK -> DATA0 -> ACK/NACK to
DATAN -> ACK/NACK

I2C bus is in write state and the same device address

DATA0 ->

ACK/NACK to

DATAN ->

ACK/NACK

Setup I2C slave write data.

Write AUX address register (0x108) with device address.

Write the data to be transmitted into AUX write FIFO register (0x104).

Issue write command and data length to transmit transaction by writing into AUX command register (0x100).

Bits [3:0] represent length field.

Write with MOT = 0.

START ->

CMD ->

ADDRESS ->

LENGTH ->

D0 to DN ->

STOP

I2C bus is IDLE or different I2C device address.

START ->

START/RS ->

DEVICE_ADDR ->

WR ->

ACK/NACK ->

DATA0 ->

ACK/NACK to

DATAN ->

ACK/NACK ->

STOP

I2C bus is in write state and the same I2C device address.

DATA0 ->

ACK/NACK to

DATAN ->

ACK/NACK ->

STOP

Setup I2C slave write data and stop the I2C bus after the current transaction.

Write the AUX address register (0x108) with device address.

Write the data to be transmitted into AUX write FIFO register (0x104).

Issue write command and data length to transmit transaction by writing into AUX command register (0x100).

Bits [3:0] represent length field.

Read with MOT = 1.

START ->

CMD ->

ADDRESS ->

LENGTH ->

STOP

I2C bus is IDLE or different I2C device address.

START ->

START/RS ->

DEVICE_ADDR ->

RD ->

ACK/NACK ->

DATA0 ->

ACK/NACK to

DATAN ->

ACK/NACK

I2C bus is in write state and the same I2C device address.

DATA0 ->

ACK/NACK to

DATAN ->

ACK/NACK

Setup I2C slave read data.

Write AUX address register (0x108) with device address.

Issue read command and data length to transmit transaction by writing into AUX command register (0x100).

Bits [3:0] represent the length field.

Read with MOT = 0.

START ->

CMD ->

ADDRESS ->

LENGTH ->

D0 to DN ->

STOP

I2C bus is IDLE or different I2C device address.

START ->

START/RS ->

DEVICE_ADDR ->

RD ->

ACK/NACK ->

DATA0 ->

ACK/NACK to

DATAN ->

ACK/NACK ->

STOP

I2C bus is in write state and the same I2C device address.

DATA0 ->

ACK/NACK to

DATAN ->

ACK/NACK ->

STOP

Setup I2C slave read data and stop the I2C bus after the current transaction.

Write AUX address register (0x108) with device address.

Issue read command and data length to transmit transaction by writing into AUX command register (0x100).

Bits [3:0] represent the length field.

 

Write status with MOT = 1.

START ->

CMD ->

ADDRESS ->

STOP

No transaction

Status of previous write command that was deferred or partially ACKED.

Write AUX address register (0x108) with device address.

Issue status update command to transmit transaction by writing into AUX command register (0x100)

Bit [12] must be set to 1.

Write status with MOT = 0.

START ->

CMD ->

ADDRESS ->

STOP

Forces a STOP and the end of write burst.

Status of previous write command that was deferred or partially ACKED.

MOT = 0 ensures the bus returns to IDLE at the end of the burst.

Write AUX address register (0x108) with device address.

Issue status update command to transmit transaction by writing into AUX command register (0x100).

Bit [12] must be set to 1.