Comparison of PS SYSMON and PL SYSMON

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The notable differences between the PS SYSMON and the PL SYSMON are the programming bus interfaces, sampling rates, and analog input signal sources. The differences are listed in Table: PS SYSMON and PL SYSMON Comparison.

Table 9-1:      PS SYSMON and PL SYSMON Comparison

Function

PS SYSMON

PL SYSMON

Sampling frequency

1 M samples per second.

200K samples per second.

Voltage reference

Internal.

Internal or external (VREFP, VREFN).

Programming interfaces

APB on AXI interconnect.
Includes DAP controller via JTAG.

APB/AXI interconnect.
DRP (PL configuration required).
I2C/PMBus.
PL JTAG controller.

Power domain

LPD.

PLPD.

Temperature sensors with OT

Temp_LPD near the RPU MPCore.

Temp_FPD near the APU MPCore.

Temp_PL near the PL SYSMON unit.

On-chip supply sensors

Three PS internal voltage nodes.
Three I/O voltage nodes.

Three PS internal voltage nodes.
Three PL internal voltage nodes.
Four PL internal VUSER nodes.

PL external sensor channels

None.

16 signal pairs; VAUXP, and VAUXN(2).
One set of dedicated pins, VP and VN(2).

PL user inputs

None.

Four, full featured.

Event driven trigger

AMS.PS_SYSMON_CONTROL_STATUS

CONVST start signal input.(1)

EOS, EOC

AMS.ISR_1 [eos], [eoc] interrupts.

EOS, EOC signals to PL fabric.(1)

Reset (see Reset Sources)

POR, write to VP_VN register, AMS.PS_SYSMON_CONTROL_STATUS.

RESET pin, write to VP_VN register.

Notes:

1.This function requires the SYSMONE4 primitive to be instantiated by the bitstream for the PL. The instantiation disconnects the PL SYSMON unit from the PS, and provides a slave bus interface and the other system signals for the PL fabric.

2.The VAUXP/VAUXN, and VN/VP analog signals are connected to device pins by instantiating the SYSMONE4 primitive.