Components

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This Figure shows where the debug infrastructure is located in the PS. It provides a conceptual view. The four ETMs next to the APU MPCore CPUs and their four CTIs and one CTM are inside the APU block; the two ETMs next to the RPU MPCore CPUs and their two CTIs and one CTM are inside the RPU block. The debug infrastructure (This Figure) is split into two power domains (gray for low power). As mentioned above, this figure is intended to show a conceptual view of the debug infrastructure. It is not detailed enough to provide exact connections. In particular, JTAG connections have been abstracted. Please refer to This Figure for a more detailed diagram of the JTAG Chain connectivity.

Figure 39-4:      CoreSight Debug Block Diagram

X-Ref Target - Figure 39-4

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