Configuration Control (APB Interface)

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The attributes for the integrated block for PCIe (Endpoint or Root Port mode) are configured through the programmable configuration and status registers (CSR) accessible through the APB interface. APB interface uses the apb_clk, which is asynchronous to the other clocks. It is a 32-bit wide address and 32-bit wide data bus interface.

The integrated block for PCIe attributes are used to set up the mode of operation (Root Port or Endpoint), the list of capabilities and address pointers and so on. A detailed list of these attributes is available in the PCIE_ATTRIB register set in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].