The CAN controller enters configuration mode, irrespective of the operation mode, when any of the following actions are performed.
•Writing a 0 to the CEN bit in the SRR register.
•Writing a 1 to the SRST bit in the SRR register. The controller enters configuration mode immediately following the software reset.
•Driving a 1 on the reset input controlled through the SLCR. The controller continues to be in reset as long as reset = 1. The controller enters configuration mode after reset is negated to 0.
In configuration mode the following apply.
•The CAN controller loses synchronization with the CAN bus and drives a constant recessive bit on the bus line.
•The error count register (ECR) is reset.
•The error status register (ESR) is reset.
•The bit timing register (BTR) and baud-rate prescaler register (BRPR) can be modified.
•The CAN controller does not receive any new messages.
•The CAN controller does not transmit any messages. Messages in the TXFIFO and the TXHPB are appended. These packets are sent when normal operation is resumed.
•Reads from the RXFIFO can be performed.
•Writes to the TXFIFO and TXHPB can be performed (provided the snoop bit is not set).
•Interrupt status register bits ARBLST, TXOK, RXOK, RXOFLW, ERROR, BSOFF, SLP, and WKUP can be cleared.
•Interrupt status register bits RXNEMP and RXUFLW can be set due to RXFIFO read operations.
•Interrupt status register bits TXBFLL and TXFLL and status register bits TXBFLL and TXFLL can be set due to write operations to the TXHPB and TXFIFO, respectively.
•Interrupts are generated if the corresponding bits in the interrupt enable register (IER) are 1.
•All configuration registers are accessible.
When in configuration mode, the CAN controller stays in this mode until the CEN bit in the SRR register is set to 1. After the CEN bit is set to 1, the CAN controller waits for a sequence of 11 recessive bits before exiting configuration mode.
The CAN controller enters normal, loopback, snoop, or sleep modes from configuration mode, depending on the LBACK, snoop, and sleep bits in the MSR register.