Configuration Request Retry Status

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

In cases where an Endpoint is not ready to respond, a configuration request retry status (CRS) response is issued to incoming PCIe configuration requests.

Note:   In this section, an Endpoint refers to the Endpoints that would be connected to a Zynq UltraScale+ MPSoC operating as a Root.

The PCIe Root Port CRS software visibility is controlled by the PCIE_ATTRIB.ATTR_79 bit [5]. If the CRS software visibility is enabled, then reads targeting DW0 in configuration space (Device ID: Vendor ID) result in, the AXI response OKAY with AXI data = 0xFFFF0001 (this special data means that the device has issued a CRS status).

If the CRS software visibility is not enabled, the AXI-PCIe bridge continues to retry the transaction until a status other than CRS is returned. However the transaction will be aborted with DECERR if it fails to succeed after being attempted for >1 second (the longest time period that a PCIe device is permitted to return CRS status).