Configure Clocks

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

When the reference clock frequency, GEM_REF_CLK is sourced from the PS clock unit, its frequency is controlled by the CRL_APB.GEM_TSU_REF_CTRL register.

Note:   The GEM_TSU_REF_CTRL register divisor fields are only applicable when the clock is set to MIO.