Configure Rx queue pointers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

1.Write Address to:

gem0_rm.receive_q_ptr  

gem0_rm.receive_q1_ptr

2.Configure screening type2 register0 to check IPv4 ether type ID (0x0800).

3.Write ethertype_enable bit and queue number as 1 in gem. screening_type_2_register_0.

4.Write EtherType compare value for your type ID, say, 0x0800 in gem.screening_type_2_ethertype_reg_0

5.Enable receive bit in the gem.network_control_register

Note:   When a screener is matched, the received frame will be routed to a queue defined inside bits 3:0 of the screener register. Unmatched frames are routed to queue 0.

In the receive direction, each data packet is written to external AHB/AXI data buffers in the order that it is received. There are separate receive buffer queue base address registers for each queue. Every received packet will pass through a programmable screening algorithm which will allocate to that frame a queue to route it to.

The user interface to the screener is via two banks of programmable registers, screener type match registers 1 and 2. Screener type 1 registers allow the user to route received frames based on particular IP and UDP fields extracted from the received frame. These fields are DS, TC, and/or the UDP destination port. These fields are compared against the values stored in the each of the screener type 1 match registers.

If the result of this comparison is positive, then the received frame is routed to the priority queue specified in that screener type 1 register. The number of type 1 screener is determined by a define in the gem defines file. Screener Type 2 match registers operate independently and offer additional match capabilities.