Configure the Controller

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
Release Date
2.3 English

The following example describes a typical programming sequence for configuration of the controller. Refer to register details for further details on the controller registers.

1.Program the network configuration register (gem.network_config). The network configuration register is used to set the mode of operation.


a.Enable full duplex. Write a 1 to the gem.network_config[full_duplex] bit.

b.Enable gigabit mode. Write a 1 to the gem.network_config[gigabit_mode_enable] bit.

c.Enable reception of broadcast or multicast frames. Write a 0 to the gem.network_config[no_broadcast] register to enable broadcast frames and write a 1 to the gem.network_config[multicast_hash_en] bit to enable multicast frames.

d.Enable promiscuous mode. Write a 1 to the gem.network_config[copy_all_frames] bit.

e.Enable TCP/IP checksum offload feature on receive. Write a 1 to the gem.network_config[receive_checksum_offload_enable] bit.

f.Enable pause frames. Write a 1 to gem.network_config[pause_enable] bit.

g.Set the MDC clock divisor. Write the appropriate MDC clock divisor to the gem.network_config[mdc_clock_division] bit.

2.Set the MAC address. Write to the gem.spec_add1_bottom and gem.spec_add1_top registers.

The least significant 32 bits of the MAC address go to gem.spec_add1_bottom and the most significant 16 bits go to gem.spec_add1_top.

3.Program the DMA configuration register (gem.dma_config).

a.Set the receive buffer size to 1,600 bytes. Write a value of 8'h19 to the gem.dma_config[rx_buf_size] bit field.

Note:   For Jumbo packet support set the receive buffer size to 10,304 bytes. Write a value of 8'h0A1 to the gem.dma_config[rx_buf_size] bit field.

b.Set the receiver packet buffer memory size to the full configured addressable space of 32 KB. Write 2'b11 to the gem.dma_config[rx_pbuf_size] bit field.

c.Set the transmitter packet buffer memory size to the full configured addressable space of 32 KB. Write a 1 to the gem.dma_config[tx_pbuf_size] bit.

d.Enable TCP/IP checksum generation offload on the transmitter. Write a 1 to the gem.dma_config[tx_pbuf_tcp_en] bit.

e.Configure for a little endian system. Write a 0 to the gem.dma_config[endian_swap_packet] bit.

f.Configure AXI fixed burst length. Write 5'h10 to the gem.dma_config[amba_burst_length] bit field to use INCR16 AXI burst for higher performance.

4.Program the network control register (gem.network_control).

a.Enable the MDIO. Write a 1 to the gem.network_control[man_port_en] bit.

b.Enable the transmitter. Write a 1 to the gem.network_control[enable_transmit] bit.

c.Enable the receiver. Write a 1 to the gem.network_control[enable_receive] bit.