Configure the PHY

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PHY connected to the controller is initialized through the available MDIO interface using the PHY management register (gem.phy_management).

Writing to this register starts a shift operation and is signaled as complete when the bit gem.network_status[man_done] is set.

The MDIO interface clock (MDC) for gigabit Ethernet is generated by dividing down the LPD_LSBUS_CLK clock.

 

TIP:   MDC is active only during MDIO read or write operations while the PHY registers are read or written.

The MDC must not exceed 2.5 MHz as defined by IEEE Std 802.3. The gem.network_config[mdc_clock_division] bit field is used to set the divisor for the IOU_SWITCH_CLK clock.