Control Logic

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The control logic contains the control register and the mode register that are used to select the various operating modes of the UART.

The control register enables, disables, and issues soft resets to the receiver and transmitter modules. In addition, it restarts the receiver timeout period and controls the transmitter break logic. The receive line break detection must be implemented in Software. It is indicated by a frame error followed by one or more zero bytes in the RXFIFO.

The mode register selects the clock used by the baud rate generator. It also selects the bit length, parity bit, and stop bit used by the transmitted and received data. In addition, it selects the mode of operation of the UART, switching between normal UART mode, automatic echo, local loopback, or remote loopback, as required.