Control Register

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The JTAG control register, JTAG_CTRL, enables the PL TAP and Arm DAP controllers onto the JTAG chain (the PS TAP controller is always present). The control bits are listed in Table: PS TAP Controller JTAG Control Register. This register is reset by a system and POR. Regardless of these bit settings, the chain length remains at 12 bits.

Table 39-5:      PS TAP Controller JTAG Control Register

Bit

Value

Description

31:2

Reserved

Reads 0.

1

Arm DAP

Write 1 to enable the Arm DAP controller.

0

PL TAP

Write 1 to enable the PL TAP controller.