Control Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The scan clear control and status registers are in the PMU local register set and are only accessible by the PMU processor. These control and status registers are used by the PMU user firmware.

LOGCLR_TRIG starts the scan clear operations (wo)

LOGCLR_ACK indicates completion of the scan clear operation (ro)

SERV_LOGCLR_ERR used by the PMU code to log scan clear errors (rw)

When a scan clear engine is started, the completion status signal from the engine transitions from 1 to 0. This signal, which is routed directly to a PMU LOGCLR_ACK register, communicates the completion status of the engine to the PMU. When a scan clear engine finishes its operation, its completion status bit toggles from 0 to 1 generating an interrupt to the PMU. The pass/fail status of the clearing operation can be checked by the bits in the PMU LOGCLR_STATUS global register that are directly driven by the pass/fail status of the engine.

The CSU only starts scan clear engines under a security lock-down scenario and there is no functional requirement for the CSU to check the pass/fail status or the completion status of the clearing operation.

For increased safety, the scan clear trigger signal from the hardware can be gated off during normal system operation using the PMU_Global.SAFETY_GATE [Scan_Enable] register bit.

The PMU user firmware can accumulate failures in the PMU_Local.SERV_LOGCLR_ERR register (reset only by a POR). This register is write protected using the PMU_Global.SAFETY_GATE [PMU_LOGCLR_Enable] register bit.

The bit assignments for the trigger and acknowledge registers are listed in Table: Scan Clear TRIG and ACK Register Bit Fields.

Table 39-16:      Scan Clear TRIG and ACK Register Bit Fields

Bit

Bit Field

System Element                     

0

ACPU0     

 APU core 0                        

1

ACPU1     

APU core 1

2

ACPU2     

APU core 2

3

ACPU3     

APU core 3

6

PP0       

 GPU pixel processor 0             

7

PP1       

GPU pixel processor 1

10

RPU       

 RPU                               

12

USB0      

 USB controller 0                  

13

USB1      

USB controller 1

16

LP        

 LPD except PMU, RPU, and USBs

17

FP        

 FPD except APU cores, and GPU