Controller Hold Signal

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The hold signal is not supported by the generic Quad-SPI controller. In dual- or single-bit modes, the hold signal is tied to 1. In quad mode, the hold signal is driven by the controller. When a hold operation is not used, the hold pin is driven High as expected by the SPI devices.