Controller Initialization

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The controller initialization sequence has the following phases.

PHY initialization

DRAM initialization

Data training

This Figure and This Figure show high-level illustrations of the initialization sequence of the PHY.

Figure 17-9:      PHY Initialization Sequence

X-Ref Target - Figure 17-9

X15353-phy-init1-flowchart.jpg
Figure 17-10:      PHY Initialization Sequence (Continued)

X-Ref Target - Figure 17-10

X15354-phy-init2-flowchart.jpg

Impedance calibration failures can be caused by an open or short on the PS_DDR_ZQ pin.  Double check to ensure PS_DDR_ZQ is connected to GND with a 240Ω resistor. There should be separate 240Ω resistors at the FPGA and the DRAM.