The controller initialization sequence has the following phases.
This Figure and This Figure show high-level illustrations of the initialization sequence of the PHY.
Impedance calibration failures can be caused by an open or short on the PS_DDR_ZQ pin. Double check to ensure PS_DDR_ZQ is connected to GND with a 240Ω resistor. There should be separate 240Ω resistors at the FPGA and the DRAM.