Controller Interrupt

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The generic Quad-SPI controller has a single interrupt output signal. The dma_irq signal from the DMA module is ORed with the internal interrupt (gqspi_int_irq) in the generic Quad-SPI controller, as shown in This Figure. The generic Quad-SPI interrupt register does not show the status of the DMA interrupt signal.

The following steps outline the software programming model for a DMA interrupt.

1.Enable the DMA IRQ bits[0..7] of QSPIDMA_DST_I_EN, the DMA interrupt enable register.

2.The interrupt is set due to the DMA. For example, DMA done.

3.The generic Quad-SPI controller interrupt is asserted as the DMA module asserts dma_irq signal that is ORed with the generic Quad-SPI internal interrupt signal.

4.The software reads the generic Quad-SPI interrupt status register. The generic Quad-SPI interrupt status register bits are not set because this model is for the DMA interrupt.

5.The software reads the DMA interrupt status register, the DMA done bit is set.

6.The software writes a 1 to clear the done bit of the DMA interrupt status register.

7.The dma_irq signal is deasserted and the generic Quad-SPI interrupt is immediately deasserted.

Figure 24-11:      Interrupt Mechanism

X-Ref Target - Figure 24-11

X15440-qspi-interrupt-block.jpg