Controller Status Register

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The status register provides information about the PS hardware version, device boot mode, BIST results, security gates, and controller connections to the JTAG chain as listed in Table: PS TAP Controller Status Register.

Table 39-6:      PS TAP Controller Status Register

Bit

Name

Description

31-28

PS_VERSION

Indicates the PS version, same as csu.version [ps_version] register bit

27-24

PL_FABRIC_PIPE

Indicates which of the PSTP fabric port access have a pipeline stage. See Section 6.2.1 for details.

23-20

PSTP_CTRL

Indicates the operating mode of the PSTP. See Section 6.2.1 for details.

19

MODE_IS_DFT

Indicates that the part has successfully booted in DFT mode

18

Unused

Constant 0 value.

17-14

BOOT_MODE

Device boot mode

13

CBR_DONE

Configuration BootROM (CBR) has finished running and the full JTAG instruction set is available

12

SCAN_CLEAR_FAILED

Pre-boot SCAN CLEAR function failed

11

LBIST_FAILED

Pre-boot LBIST function failed

10

BISR_FAILED

Pre-boot BISR function failed

9

PL_PWR_STS

Power status of the PL, cannot connect to the PL TAP if this bit is 0

8

FUSE_MDM_DIS

Indicates that the CSU MDM disable fuses are programmed.

7

DDR_PHY_SEC_GATE

Indicates if the DDR_PHY Security Gate is disabled.

6

PMU_MDM_SEC_GATE

PMU MDM security gate is disabled

5

PL_TAP_SEC_GATE

PL TAP security gate is disabled

4

ARM_DAP_SEC_GATE

Arm DAP security gate is disabled

3

ARM_DAP

Arm DAP is connected in the JTAG chain

2

PL_TAP

PL TAP is connected in the JTAG chain

1

0

 

0

1