CoreSight Address Map

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This section describes the CoreSight register architecture.

Each component in the RPU is allocated a 4 KB register space; outside the RPU, each component is allocated a 64 KB register space.

Within each component register space, there are fixed locations for fixed purposes.

Address 0x0 on the debug APB is a ROM table, pointing to all other components.

Each component can be accessed at two address locations on the debug APB.

°When accessed from internal using system map, paddr[31] is forced to 0.

°When accessed from external through JTAG, paddr[31] can be 1 or 0.

paddr[31]=1 and paddr[31]=0 are subject to different authentications. This is useful for preventing rogue software on the RPU or APU MPCore from interfering with CoreSight components.

CoreSight components are allocated 8 MB of address space from FE80_0000 to FEFF_FFFF. This Figure shows the detailed address space assignment for each debug component. References to the detailed address map within each component space are as follows.

DAP

Arm CoreSight SoC-400 Technical Reference Manual [Ref 39], chapter 3.

Timestamp

Arm CoreSight SoC-400 Technical Reference Manual [Ref 39], chapter 3.

Funnel

Arm CoreSight SoC-400 Technical Reference Manual [Ref 39], chapter 3.

TPIU

Arm CoreSight SoC-400 Technical Reference Manual [Ref 39], chapter 3.

CTI

Arm CoreSight SoC-400 Technical Reference Manual [Ref 39], chapter 3.

STM

Arm CoreSight STM-500 System Trace Macrocell Technical Reference Manual [Ref 44], chapter 3.

TMC

CoreSight Trace Memory Controller Technical Reference Manual [Ref 45], chapter 3.

Cortex-A53 ETM

Arm Cortex-A53 MPCore Processor Technical Reference Manual [Ref 46], chapter 13.

Cortex-R5 ETM

CoreSight ETM-R5 Technical Reference Manual [Ref 48], chapter 3.

 

 

 

 

 

Figure 39-8:      CoreSight System Debug Address Map

X-Ref Target - Figure 39-8

X15260-address_map.jpg