Cortex-A53 MPCore Processor Features

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The Cortex-A53 MPCore processor includes the following features.

AArch32 and AArch64 execution states.

All exception levels (EL0, EL1, EL2, and EL3) in each execution state.

Arm v8-A architecture instruction set including advanced SIMD, VFPv4 floating-point extensions, and cryptography extensions.

Separate 32 KB L1 caches for instruction and data.

Two-stage (hypervisor and guest stages) memory management unit (MMU).

CPU includes an in-order 8-stage pipeline with symmetric dual-issue of most instructions.

1 MB L2 cache in CCI coherency domain.

Accelerator coherency port (ACP).

128-bit AXI coherency extension (ACE) master interface to CCI.

Arm v8 debug architecture.

Configurable endianess.

Supports hardware virtualization that enables multiple software environments and their applications to simultaneously access the system capabilities.

Hardware-accelerated cryptography—3-10x better software encryption performance.

Large physical address reach enables the processor to access beyond 4 GB of physical memory.

TrustZone technology ensures reliable implementation of security applications.