The Cortex-R5F processor is a mid-range CPU for use in deeply-embedded, real-time systems. It implements the Arm v7-R architecture, and includes Thumb-2 technology for optimum code density and processing throughput. The pipeline has a single arithmetic logic unit (ALU), but implements limited dual-issuing of instructions for efficient utilization of other resources such as the register file. Interrupt latency is kept low by interrupting and restarting load-store multiple instructions, and by use of a dedicated peripheral port that enables low-latency access to an interrupt controller. The processor has tightly-coupled memory (TCM) ports for low-latency and deterministic accesses to local RAM, in addition to caches for higher performance to general memory. Error checking and correction (ECC) is used on the Cortex-R5F processor ports and in Level 1 (L1) memories to provide improved reliability and address safety-critical applications. This Figure shows the system view of the real-time processing unit.