DDR Controller Address Map

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DDR controller (DDRC) block performs the scheduling and SDRAM command generation. It holds information on the commands, and then based on the scheduling algorithms optimally schedule commands to be sent to the PHY-based on priority, bank/rank status, and DDR timing constraints.