DDR Controller Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Table 17-32:      DDR Controller Registers

Register Name

Register Description

MSTR(2)

Master register.

STAT

Operating mode status register.

MRCTRL{0:2}

Mode register read/write control register {0:2}

MRSTAT

Mode register read/write status register.

DERATEEN

Temperature derate enable register.

DERATEINT(4)

Temperature derate interval register.

PWRCTL

Low-power control register.

PWRTMG

Low-power timing register.

HWLPCTL(3)

Hardware low-power control register.

RFSHCTL0

Refresh control register 0.

RFSHCTL1

Refresh control register 1.

RFSHCTL3(2)

Refresh control register 3.

RFSHTMG

Refresh timing register.

ECCCFG0

ECC configuration register 0.

ECCCFG1(3)

ECC configuration register 1.

ECCSTAT

ECC status register.

ECCCLR

ECC clear register.

ECCERRCNT

ECC error counter register.

ECCCADDR{0:1}

ECC corrected error address register {0:1}.

ECCCSYN{0:2}

ECC corrected syndrome register {0:2}.

ECCBITMASK{0:2}

ECC corrected data bit mask register {0:2}.

ECCUADDR{0:1}

ECC uncorrected error address register {0:1}.

ECCUSYN{0:2}

ECC uncorrected syndrome register {0:2}.

ECCPOISONADDR{0:1}

ECC data poisoning address register{0:1}.

CRCPARCTL{0:2}

CRC parity control register {0:2}.

CRCPARSTAT

CRC parity status register.

INIT{0:7}(1)(2)(3)

SDRAM initialization registers {0:7}.

DIMMCTL

DIMM control register.

RANKCTL

Rank control register.

DRAMTMG{0:14}(1)(2)(4)

SDRAM timing registers {0:14}.

ZQCTL{0:2}(2)(4)

ZQ control register {0:2}.

ZQSTAT

ZQ status register.

DFITMG{0:1}(1)(2)(3)(4)

DFI timing register {0:1}.

DFILPCFG{0:1}

DFI low-power configuration register {0:1}.

DFIUPD{0:2}(3)

DFI update register {0:2}.

DFIMISC(3)

DFI miscellaneous control register.

DFITMG2(4)

DFI timing register 2.

DBICTL(1)

DM/DBI control register.

ADDRMAP{0:11}

Address map registers {0:11}.

ODTCFG(1)(4)

ODT configuration register.

ODTMAP

ODT/rank map register.

SCHED(3)

Scheduler control register.

SCHED1

Scheduler control register 1.

PERFHPR1(3)

High-priority read CAM register 1.

PERFLPR1(3)

Low-priority read CAM register 1.

PERFWR1(3)

Write CAM register 1.

PERFVPR1

Video/isochronous priority read CAM register 1.

PERFVPW1

Video/isochronous priority write CAM register 1.

DQMAP{0:5}

DQ map registers {0:5}.

DBG{0:1}

Debug register {0:1}.

DBGCAM

CAM debug register.

DBGCMD

Command debug register.

DBGSTAT

Status debug register.

SWCTL

Software register programming control enable.

SWSTA

Software register programming control status.

POISONCFG

AXI poison configuration register.

POISONSTAT

AXI poison status register.

PSTAT

Port status register.

PCCFG

Port common configuration register.

PCFGR_{0:5}

Port {0:5} configuration read register.

PCFGW_{0:5}

Port {0:5} configuration write register.

PCTRL_{0:5}

Port {0:5} control register.

PCFGQOS0_{0:5}(3)

Port {0:5} read QoS configuration register 0.

PCFGQOS1_{0:5}(3)

Port {0:5} read QoS configuration register 1.

PCFGWQOS0_{0:5}(3)

Port {0:5} write QoS configuration register 0.

PCFGWQOS1_{0:5}(3)

Port {0:5} write QoS configuration register 1.

SARBASE0

SAR base address register n.

SARSIZE0

SAR size register n.

SARBASE1

SAR base address register n.

SARSIZE1

SAR size register n.

DERATEINT_SHADOW

Temperature derate interval shadow register.

RFSHCTL0_SHADOW

Refresh control shadow register 0.

RFSHTMG_SHADOW

Refresh timing shadow register.

INIT3_SHADOW

SDRAM initialization shadow register 3.

INIT4_SHADOW

SDRAM initialization shadow register 4.

INIT6_SHADOW

SDRAM initialization shadow register 6.

INIT7_SHADOW

SDRAM initialization shadow register 7.

DRAMTMG{0:14}_SHADOW

SDRAM timing shadow registers {0:14}.

ZQCTL0_SHADOW

ZQ control shadow register 0.

DFITMG0_SHADOW

DFI timing shadow register 0.

DFITMG1_SHADOW

DFI timing shadow register 1.

DFITMG2_SHADOW

DFI timing shadow register 2.

ODTCFG_SHADOW

ODT configuration shadow register.

Notes:

1.Quasi dynamic registers group 1.

2.Quasi dynamic registers group 2.

3.Quasi dynamic registers group 3.

4.Quasi dynamic registers group 4.

5.For detailed description, see the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].