DDR Memory Controller Clock Generator

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DDR clock is used for the majority of the DDR memory controller logic. The clock generator has one 6-bit divider that connects to either the DPLL or VPLL. The DDR memory subsystem also includes six PLLs for the DRAM I/O buffers that are described in DDR Memory Controller.

The DDR memory controller clock generator is shown in This Figure.

Figure 37-6:      DDR Memory Controller Clock Generator

X-Ref Target - Figure 37-6

X19871-ddr-memory-controller.jpg